Dual gates in a thin film transistor array substrate can reduce a number of data lines, thus data signal driving chip, and its cost, can be reduced. In a conventional thin film transistor array substrate, scan lines are usually made of a first conductive layer, common lines are made of a second conductive layer. The common line overlaps with two adjacent scan lines to form two equal parasitic capacitances.
However, if there is an offset between the first conductive layer and the second conductive layer during the fabrication process, the common line and the adjacent two scan lines have different overlapping areas, resulting in unequal capacitance values of the parasitic capacitances. Thus, the charging rates of two adjacent columns of pixels are affected. If there are differences in the charging rates of the two adjacent columns of pixels, the display panel will include bright and dark stripes, and the display quality may be greatly reduced, especially in high-resolution products.
Therefore, there is room for improvement in the art.